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STK12C68-5 (SMD5962-94599)
64 Kbit (8K x 8) AutoStore nvSRAM
Features

Functional Description
The Cypress STK12C68-5 is a fast static RAM with a nonvolatile element in each memory cell. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world's most reliable nonvolatile memory. The SRAM provides unlimited read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements (the STORE operation) takes place automatically at power down. On power up, data is restored to the SRAM (the RECALL operation) from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. A hardware STORE is initiated with the HSB pin.
35 ns and 55 ns access times Hands off automatic STORE on power down with external 68 F capacitor STORE to QuantumTrapTM nonvolatile elements is initiated by software, hardware, or AutoStoreTM on power down RECALL to SRAM initiated by software or power up Unlimited Read, Write, and Recall cycles 1,000,000 STORE cycles to QuantumTrap 100 year data retention to QuantumTrap Single 5V+10% operation Military temperature 28-pin (300mil) CDIP and 28-pad LCC packages
Logic Block Diagram
A5
Quantum Trap 128 X 512 STORE ROW DECODER STATIC RAM ARRAY 128 X 512 RECALL
VCC
VCAP
A6 A7 A8 A9 A 11 A 12
POWER CONTROL STORE/ RECALL CONTROL
HSB
SOFTWARE DETECT COLUMN I/O INPUT BUFFERS COLUMN DEC
A0
- A12
DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7
A 0 A 1 A 2 A 3 A 4 A 10
OE
CE WE
Cypress Semiconductor Corporation Document Number: 001-51026 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised March 02, 2009
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STK12C68-5 (SMD5962-94599)
Pinouts
Figure 1. Pin Diagram - 28-Pin DIP Figure 2. Pin Diagram - 28-Pin LLC
Pin Definitions
Pin Name A0-A12 DQ0-DQ7 WE CE OE VSS VCC HSB W E G Alt IO Type Input Input Input Input Ground Description Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM. Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO pins is written to the specific address location. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. Deasserting OE HIGH causes the IO pins to tri-state. Ground for the Device. The device is connected to ground of the system.
Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.
Power Supply Power Supply Inputs to the Device. Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull up resistor keeps this pin high if not connected (connection optional). Power Supply AutoStore Capacitor. Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile elements.
VCAP
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Device Operation
The STK12C68-5 nvSRAM is made up of two functional components paired in the same physical cell. These are an SRAM memory cell and a nonvolatile QuantumTrap cell. The SRAM memory cell operates as a standard fast static RAM. Data in the SRAM is transferred to the nonvolatile cell (the STORE operation) or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture enables the storage and recall of all cells in parallel. During the STORE and RECALL operations, SRAM Read and Write operations are inhibited. The STK12C68-5 supports unlimited reads and writes similar to a typical SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to one million STORE operations. During normal operation, the device draws current from VCC to charge a capacitor connected to the VCAP pin. This stored charge is used by the chip to perform a single STORE operation. If the voltage on the VCC pin drops below VSWITCH, the part automatically disconnects the VCAP pin from VCC. A STORE operation is initiated with power provided by the VCAP capacitor. Figure 3 shows the proper connection of the storage capacitor (VCAP) for automatic store operation. A charge storage capacitor between 68 F and 220 F (+20%) rated at 6V must be provided. The voltage on the VCAP pin is driven to 5V by a charge pump internal to the chip. A pull up is placed on WE to hold it inactive during power up. Figure 3. AutoStore Mode
SRAM Read
The STK12C68-5 performs a Read cycle whenever CE and OE are LOW while WE and HSB are HIGH. The address specified on pins A0-12 determines the 8,192 data bytes accessed. When the Read is initiated by an address transition, the outputs are valid after a delay of tAA (Read cycle 1). If the Read is initiated by CE or OE, the outputs are valid at tACE or at tDOE, whichever is later (Read cycle 2). The data outputs repeatedly respond to address changes within the tAA access time without the need for transitions on any control input pins, and remains valid until another address change or until CE or OE is brought HIGH, or WE or HSB is brought LOW.
SRAM Write
A Write cycle is performed whenever CE and WE are LOW and HSB is HIGH. The address inputs must be stable prior to entering the Write cycle and must remain stable until either CE or WE goes HIGH at the end of the cycle. The data on the common IO pins DQ0-7 are written into the memory if it has valid tSD, before the end of a WE controlled Write or before the end of an CE controlled Write. Keep OE HIGH during the entire Write cycle to avoid data bus contention on common IO lines. If OE is left LOW, internal circuitry turns off the output buffers tHZWE after WE goes LOW.
AutoStore Operation
The STK12C68-5 stores data to nvSRAM using one of three storage operations: 1. Hardware store activated by HSB 2. Software store activated by an address sequence 3. AutoStore on device power down AutoStore operation is a unique feature of QuantumTrap technology and is enabled by default on the STK12C68-5.
In system power mode, both VCC and VCAP are connected to the +5V power supply without the 68 F capacitor. In this mode, the AutoStore function of the STK12C68-5 operates on the stored system charge as power goes down. The user must, however, guarantee that VCC does not drop below 3.6V during the 10 ms STORE cycle. To reduce unnecessary nonvolatile stores, AutoStore, and Hardware Store operations are ignored, unless at least one Write operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a Write operation has taken place. An optional pull up resistor is shown connected to HSB. The HSB signal is monitored by the system to detect if an AutoStore cycle is in progress.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Figure 4. AutoStore Inhibit Mode During any STORE operation, regardless of how it is initiated, the STK12C68-5 continues to drive the HSB pin LOW, releasing it only when the STORE is complete. After completing the STORE operation, the STK12C68-5 remains disabled until the HSB pin returns HIGH. If HSB is not used, it is left unconnected.
Hardware RECALL (Power Up)
During power up or after any low power condition (VCC < VRESET), an internal RECALL request is latched. When VCC once again exceeds the sense voltage of VSWITCH, a RECALL cycle is automatically initiated and takes tHRECALL to complete. If the STK12C68-5 is in a Write state at the end of power up RECALL, the SRAM data is corrupted. To help avoid this situation, a 10 Kohm resistor is connected either between WE and system VCC or between CE and system VCC.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK12C68-5 software STORE cycle is initiated by executing sequential CE controlled Read cycles from six specific address locations in exact order. During the STORE cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. When a STORE cycle is initiated, input and output are disabled until the cycle is completed. Because a sequence of Reads from specific addresses is used for STORE initiation, it is important that no other Read or Write accesses intervene in the sequence. If they intervene, the sequence is aborted and no STORE or RECALL takes place. To initiate the software STORE cycle, the following Read sequence is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ 4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0F, Initiate STORE cycle The software sequence is clocked with CE controlled Reads or OE controlled Reads. When the sixth address in the sequence is entered, the STORE cycle commences and the chip is disabled. It is important that Read cycles and not Write cycles are used in the sequence. It is not necessary that OE is LOW for a valid sequence. After the tSTORE cycle time is fulfilled, the SRAM is again activated for Read and Write operation.
If the power supply drops faster than 20 us/volt before Vcc reaches VSWITCH, then a 2.2 ohm resistor must be connected between VCC and the system supply to avoid momentary excess of current between VCC and VCAP.
AutoStore Inhibit Mode
If an automatic STORE on power loss is not required, then VCC is tied to ground and +5V is applied to VCAP (Figure 4). This is the AutoStore Inhibit mode, where the AutoStore function is disabled. If the STK12C68-5 is operated in this configuration, references to VCC are changed to VCAP throughout this data sheet. In this mode, STORE operations are triggered through software control or the HSB pin. To enable or disable Autostore using an IO port pin see Preventing Store on page 5. It is not permissible to change between these three options "on the fly".
Hardware STORE (HSB) Operation
The STK12C68-5 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin is used to request a hardware STORE cycle. When the HSB pin is driven LOW, the STK12C68-5 conditionally initiates a STORE operation after tDELAY. An actual STORE cycle only begins if a Write to the SRAM takes place since the last STORE or RECALL cycle. The HSB pin also acts as an open drain driver that is internally driven LOW to indicate a busy condition, while the STORE (initiated by any means) is in progress. SRAM Read and Write operations, that are in progress when HSB is driven LOW by any means, are given time to complete before the STORE operation is initiated. After HSB goes LOW, the STK12C68-5 continues SRAM operations for tDELAY. During tDELAY, multiple SRAM Read operations take place. If a Write is in progress when HSB is pulled LOW, it allows a time, tDELAY to complete. However, any SRAM Write cycles requested after HSB goes LOW are inhibited until HSB returns HIGH. Document Number: 001-51026 Rev. **
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of Read operations in a manner similar to the software STORE initiation. To initiate the RECALL cycle, the following sequence of CE controlled Read operations is performed: 1. Read address 0x0000, Valid READ 2. Read address 0x1555, Valid READ 3. Read address 0x0AAA, Valid READ Page 4 of 18
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STK12C68-5 (SMD5962-94599)
4. Read address 0x1FFF, Valid READ 5. Read address 0x10F0, Valid READ 6. Read address 0x0F0E, Initiate RECALL cycle Internally, RECALL is a two step procedure. First, the SRAM data is cleared; then, the nonvolatile information is transferred into the SRAM cells. After the tRECALL cycle time, the SRAM is again ready for Read and Write operations. The RECALL operation does not alter the data in the nonvolatile elements. The nonvolatile data can be recalled an unlimited number of times. Figure 5. Current Versus Cycle Time (Read)
Data Protection
The STK12C68-5 protects data from corruption during low voltage conditions by inhibiting all externally initiated STORE and Write operations. The low voltage condition is detected when VCC is less than VSWITCH. If the STK12C68-5 is in a Write mode (both CE and WE are low) at power up after a RECALL or after a STORE, the Write is inhibited until a negative transition on CE or WE is detected. This protects against inadvertent writes during power up or brown out conditions.
Figure 6. Current Versus Cycle Time (Write)
Noise Considerations
The STK12C68-5 is a high speed memory. It must have a high frequency bypass capacitor of approximately 0.1 F connected between VCC and VSS, using leads and traces that are as short as possible. As with all high speed CMOS ICs, careful routing of power, ground, and signals reduce circuit noise.
Hardware Protect
The STK12C68-5 offers hardware protection against inadvertent STORE operation and SRAM Writes during low voltage conditions. When VCAPPreventing Store
The STORE function is disabled by holding HSB high with a driver capable of sourcing 30 mA at a VOH of at least 2.2V, because it must overpower the internal pull down device. This device drives HSB LOW for 20 s at the onset of a STORE. When the STK12C68-5 is connected for AutoStore operation (system VCC connected to VCC and a 68 F capacitor on VCAP) and VCC crosses VSWITCH on the way down, the STK12C68-5 attempts to pull HSB LOW. If HSB does not actually get below VIL, the part stops trying to pull HSB LOW and abort the STORE attempt.
Low Average Active Power
CMOS technology provides the STK12C68-5 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. Figure 5 and Figure 6 shows the relationship between ICC and Read or Write cycle time. Worst case current consumption is shown for both CMOS and TTL input levels (commercial temperature range, VCC = 5.5V, 100% duty cycle on chip enable). Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK12C68-5 depends on the following items:

The duty cycle of chip enable The overall cycle rate for accesses The ratio of Reads to Writes CMOS versus TTL input levels The operating temperature The VCC level
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Best Practices
nvSRAM products have been used effectively for over 15 years. While ease-of-use is one of the product's main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:

Power up boot firmware routines must rewrite the nvSRAM into the desired state. While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). The Vcap value specified in this data sheet includes a minimum and a maximum value size. The best practice is to meet this requirement and not exceed the maximum Vcap value because the higher inrush currents may reduce the reliability of the internal pass transistor. Customers who want to use a larger Vcap value to make sure there is extra store charge must discuss their Vcap size selection with Cypress.
The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer's sites sometimes reprograms these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A. The end product's firmware must not assume that an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on must always program a unique NV pattern (for example, complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
Table 1. Hardware Mode Selection CE H L L X L WE X H L X H HSB H H H L H A12-A0 X X X X 0x0000 0x1555 0x0AAA 0x1FFF 0x10F0 0x0F0F 0x0000 0x1555 0x0AAA 0x1FFF 0x10F0 0x0F0E Mode Not Selected Read SRAM Write SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL IO Output High Z Output Data Input Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Output Data Output Data Output Data Output Data Output Data Output High Z Power Standby Active[3] Active ICC2[1] Active ICC2[2, 3]
L
H
H
Active[2, 3]
Notes 1. HSB STORE operation occurs only if an SRAM Write is done since the last nonvolatile cycle. After the STORE (If any) completes, the part goes into standby mode, inhibiting all operations until HSB rises. 2. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle. 3. IO state assumes OE < VIL. Activation of nonvolatile cycles does not depend on state of OE.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Temperature under Bias ............................. -55C to +125C Voltage on Input Relative to GND.....................-0.5V to 7.0V Voltage on Input Relative to Vss............ -0.6V to VCC + 0.5V Range Military Ambient Temperature -55C to +125C VCC 4.5V to 5.5V Voltage on DQ0-7 or HSB .......................-0.5V to Vcc + 0.5V Power Dissipation.......................................................... 1.0W DC output Current (1 output at a time, 1s duration) .... 15 mA
Operating Range
DC Electrical Characteristics
Parameter ICC1 Description Average VCC Current
Over the operating range (VCC = 4.5V to 5.5V) [4] Test Conditions tRC = 35 ns tRC = 55 ns Dependent on output loading and cycle rate. Values obtained without output loads. IOUT = 0 mA. All Inputs Do Not Care, VCC = Max Average current for duration tSTORE Min Max 75 55 Unit mA mA
ICC2 ICC3
Average VCC Current during STORE
3 10
mA mA
Average VCC Current at WE > (VCC - 0.2V). All other inputs cycling. tRC= 200 ns, 5V, 25C Dependent on output loading and cycle rate. Values obtained without output loads. Typical Average VCAP Current All Inputs Do Not Care, VCC = Max during AutoStore Cycle Average current for duration tSTORE VCC Standby Current tRC = 35 ns, CE > VIH (Standby, Cycling TTL tRC = 55 ns, CE > VIH Input Levels) VCC Standby Current CE > (VCC - 0.2V). All others VIN < 0.2V or > (VCC - 0.2V). Standby current level after nonvolatile cycle is complete. Inputs are static. f = 0 MHz. -1 -5 2.2 VSS - 0.5 IOUT = -4 mA IOUT = 8 mA IOUT = 3 mA Between Vcap pin and Vss, 6V rated. 68 F +20% nom. 54 2.4
ICC4 ISB1[5] ISB2 [5] IIX IOZ VIH VIL VOH VOL VBL VCAP
2 24 19 2.5
mA mA mA mA
Input Leakage Current VCC = Max, VSS < VIN < VCC Off State Output VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL Leakage Current Input HIGH Voltage Input LOW Voltage Output HIGH Voltage Output LOW Voltage Logic `0' Voltage on HSB Output Storage Capacitor
+1 +5 VCC + 0.5 0.8 0.4 0.4 260
A A V V V V V F
Notes 4. VCC reference levels throughout this data sheet refer to VCC if that is where the power supply connection is made, or VCAP if VCC is connected to ground. 5. CE > VIH does not produce standby current levels until any nonvolatile cycle in progress has timed out.
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STK12C68-5 (SMD5962-94599)
Data Retention and Endurance
Parameter DATAR NVC Description Data Retention Nonvolatile STORE Operations Min 100 1,000 Unit Years K
Capacitance
Parameter CIN COUT
In the following table, the capacitance parameters are listed.[6] Description Input Capacitance Output Capacitance TA = 25C, f = 1 MHz, VCC = 0 to 3.0 V Test Conditions Max 8 7 Unit pF pF
Thermal Resistance
Parameter
In the following table, the thermal resistance parameters are listed.[6] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 28-CDIP 28-LCC TBD TBD TBD TBD Unit C/W C/W
JA JC
Figure 7. AC Test Loads R1 963 5.0V Output 30 pF R2 512 Output 5 pF R2 512 5.0V R1 963 For Tri-state Specs
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V Input Rise and Fall Times (10% to 90%) ...................... <5 ns Input and Output Timing Reference Levels .......................1.5
Note 6. These parameters are guaranteed by design and are not tested.
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STK12C68-5 (SMD5962-94599)
AC Switching Characteristics
SRAM Read Cycle
Parameter Cypress Parameter tACE tRC
[7]
35 ns Alt Description Chip Enable Access Time Read Cycle Time Address Access Time Output Enable to Data Valid Output Hold After Address Change Chip Enable to Output Active Chip Disable to Output Inactive Output Enable to Output Active Output Disable to Output Inactive Chip Enable to Power Active Chip Disable to Power Standby 0 35 0 10 0 5 5 10 0 35 35 15 5 5 Min Max 35 55 Min
55 ns Max 55 55 35 Unit ns ns ns ns ns ns 12 12 55 ns ns ns ns ns
tELQV tAVAV, tELEH tAVQV tGLQV tAXQX tELQX tEHQZ tGLQX tGHQZ tELICCH tEHICCL
[9]
tAA [8] tDOE tOHA [8] tLZCE tLZOE tPU [6] tPD [6] tHZCE [9]
[9]
tHZOE [9]
Switching Waveforms
Figure 8. SRAM Read Cycle 1: Address Controlled [7, 8]
Figure 9. SRAM Read Cycle 2: CE and OE Controlled [7]
Notes 7. WE and HSB must be High during SRAM Read cycles. 8. Device is continuously selected with CE and OE both Low. 9. Measured 200 mV from steady state output voltage.
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STK12C68-5 (SMD5962-94599)
SRAM Write Cycle
Parameter Cypress Alt Parameter tWC tAVAV tPWE tWLWH, tWLEH tSCE tELWH, tELEH tSD tDVWH, tDVEH tHD tWHDX, tEHDX tAW tAVWH, tAVEH tSA tAVWL, tAVEL tHA tWHAX, tEHAX tHZWE [9,10] tWLQZ tLZWE [9] tWHQX 35 ns Description Write Cycle Time Write Pulse Width Chip Enable To End of Write Data Setup to End of Write Data Hold After End of Write Address Setup to End of Write Address Setup to Start of Write Address Hold After End of Write Write Enable to Output Disable Output Active After End of Write Min 35 25 25 12 0 25 0 0 13 5 5 Max Min 55 45 45 25 0 45 0 0 15 55 ns Max Unit ns ns ns ns ns ns ns ns ns ns
Switching Waveforms
Figure 10. SRAM Write Cycle 1: WE Controlled [11, 12]
tWC
ADDRESS
tSCE
CE
tHA
tAW tSA
WE
tPWE tSD tHD
DATA IN
DATA VALID
tHZWE
DATA OUT PREVIOUS DATA
HIGH IMPEDANCE
tLZWE
Figure 11. SRAM Write Cycle 2: CE Controlled [11, 12]
tWC
ADDRESS
CE
tSA tAW tPWE
tSCE
tHA
WE
tSD
DATA IN DATA VALID
tHD
DATA OUT
HIGH IMPEDANCE
Notes 10. If WE is Low when CE goes Low, the outputs remain in the high impedance state. 11. HSB must be high during SRAM Write cycles. 12. CE or WE must be greater than VIH during address transitions.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
AutoStore or Power Up RECALL
Parameter tHRECALL [13] tDELAY [9, 15] VSWITCH VRESET tVCCRISE tVSBL[11] Alt tRESTORE tHLQZ , tBLQZ Description Power up RECALL Duration STORE Cycle Duration Time Allowed to Complete SRAM Cycle Low Voltage Trigger Level Low Voltage Reset Level VCC Rise Time Low Voltage Trigger (VSWITCH) to HSB Low 150 300 1 4.0 4.5 3.9 STK12C68-5 Min Max 550 10 Unit s ms s V V s ns
tSTORE [14, 15, 16] tHLHZ
Switching Waveform
Figure 12. AutoStore/Power Up RECALL
WE
Notes 13. tHRECALL starts from the time VCC rises above VSWITCH. 14. CE and OE low for output behavior. 15. CE and OE low and WE high for output behavior. 16. HSB is asserted low for 1us when VCAP drops through VSWITCH. If an SRAM Write has not taken place since the last nonvolatile cycle, HSB is released and no store takes place.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Software Controlled STORE/RECALL Cycle
The software controlled STORE/RECALL cycle follows. [18] Parameter tRC[14] tSA[17] tCW[17] tHACE[17] tRECALL tAVAV tAVEL tELEH tELAX Alt Description STORE/RECALL Initiation Cycle Time Address Setup Time Clock Pulse Width Address Hold Time RECALL Duration Figure 13. CE Controlled Software STORE/RECALL Cycle [18] 35 ns Min 35 0 25 20 20 Max 55 0 30 20 20 55 ns Min Max Unit ns ns ns ns s
Switching Waveform
tRC
ADDRESS ADDRESS # 1
tRC
ADDRESS # 6
tSA
CE
tSCE
tHACE
OE
t STORE / t RECALL
DQ (DATA) DATA VALID DATA VALID
HIGH IMPEDANCE
Notes 17. The software sequence is clocked on the falling edge of CE without involving OE (double clocking aborts the sequence). 18. The six consecutive addresses must be read in the order listed in Table 1 on page 6. WE must be HIGH during all six consecutive cycles.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Hardware STORE Cycle
Parameter tSTORE [9, 14] tDHSB [14, 19] tPHSB tHLBL tHLHZ tHLHX Alt Description STORE Cycle Duration STK12C68-5 Min Max 10 700 15 300 Unit ms ns ns ns
tRECOVER, tHHQX Hardware STORE High to Inhibit Off Hardware STORE Pulse Width Hardware STORE Low to STORE Busy
Switching Waveform
Figure 14. Hardware STORE Cycle
Note 19. tDHSB is only applicable after tSTORE is complete.
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Part Numbering Nomenclature STK12C68 - 5 C 35 M
Temperature Range: M - Military (-55 to 125C) Speed: 35 - 35 ns 55 - 55 ns
Package: C = Ceramic 28-pin 300 mil DIP (gold lead finish) K = Ceramic 28-pin 300 mil DIP (Solder dip finish) L = Ceramic 28-pin LLC Retention / Endurance 5 = Military (10 years or 105 cycles)
SMD5962 - 94599 01 MX X
Lead Finish A = Solder DIP lead finish C = Gold lead DIP finish X = Lead finish "A" or "C" is acceptable Case Outline X = Ceramic 28-pin 300 mil DIP Y = Ceramic 28-pin LLC
Device Class Indicator - Class M
Device Type: 01 = 55 ns 03 = 35 ns
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Ordering Information
Speed (ns) 35 Ordering Code STK12C68-5C35M STK12C68-5K35M STK12C68-5L35M 55 STK12C68-5C55M STK12C68-5K55M STK12C68-5L55M Package Diagram 001-51695 001-51695 001-51696 001-51695 001-51695 001-51696 Package Type 28-pin CDIP (300 mil) 28-pin CDIP (300 mil) 28-pin LCC (350 mil) 28-pin CDIP (300 mil) 28-pin CDIP (300 mil) 28-pin LCC (350 mil) Operating Range Military
The above table contains Final information. Contact your local Cypress sales representative for availability of these parts
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Package Diagrams
Figure 15. 28-Pin (300-Mil) Side Braze DIL (001-51695)
001-51695 **
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Package Diagrams (continued)
Figure 16. 28-Pad (350-Mil) LCC (001-51696)
1. ALL DIMENSION ARE IN INCHES AND MILLIMETERS [MIN/MAX] 2. JEDEC 95 OUTLINE# MO-041 3. PACKAGE WEIGHT : TBD
001-51696 **
Document Number: 001-51026 Rev. **
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STK12C68-5 (SMD5962-94599)
Document History Page
Document Title: STK12C68-5 (SMD5962-94599), 64 Kbit (8K x 8) AutoStore nvSRAM Document Number: 001-51026 Rev ** ECN No. 2666844 Orig. of Change GVCH/PYRS Submission Date 03/02/09 New data sheet Description of Change
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(c) Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-51026 Rev. **
Revised March 02, 2009
Page 18 of 18
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